Электронный компонент: uPSD3233A-24T1T

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1/170

November 2004

uPSD3234A, uPSD3234BV
uPSD3233B, uPSD3233BV

Flash Programmable System Devices

with 8032 Microcontroller Core and 64 Kbit SRAM

FEATURES SUMMARY

FAST 8-BIT 8032 MCU
�

40MHz at 5.0V, 24MHz at 3.3V

�

Core, 12-clocks per instruction

DUAL FLASH MEMORIES WITH MEMORY
MANAGEMENT
�

Place either memory into 8032 program
address space or data address space

�

READ-while-WRITE operation for In-
Application Programming and EEPROM
emulation

�

Single voltage program and erase

�

100K minimum erase cycles, 15-year
retention

CLOCK, RESET, AND SUPPLY
MANAGEMENT
�

SRAM is Battery Backup capable

�

Normal, Idle, and Power Down Modes

�

Power-on and Low Voltage reset
supervisor

�

Programmable Watchdog Timer

PROGRAMMABLE LOGIC, GENERAL
PURPOSE
�

16 macrocells

�

Implements state machines, glue-logic,
and so forth

COMMUNICATION INTERFACES
�

USB v1.1, low-speed 1.5Mbps, 3
endpoints

�

I

2

C Master/Slave bus controller

�

Two UARTs with independent baud rate

�

Six I/O ports with up to 46 I/O pins

�

8032 Address/Data bus available on
TQFP80 package

�

5 PWM outputs, 8-bit resolution

JTAG IN-SYSTEM PROGRAMMING
�

Program the entire device in as little as
10 seconds

Figure 1. Packages

A/D CONVERTER
�

Four channels, 8-bit resolution, 10�s

TIMERS AND INTERRUPTS
�

Three 8032 standard 16-bit timers

�

10 Interrupt sources with two external
interrupt pins

Single Supply Voltage
�

4.5 to 5.5V

�

3.0 to 3.6V

TQFP52 (T)

52-lead, Thin,

Quad Flat

TQFP80 (U)

80-lead, Thin,

Qual Flat

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

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Table 1. Device Summary

Part Number

Max

Clock
(MHz)

1st

Flash

(bytes)

2nd

Flash

(bytes)

SRAM

(bytes)

GPIO

USB

8032

Bus

V

CC

(V)

Pkg.

Temp.

uPSD3233B-40T6

40

128K

32K

8K

37

No

No

4.5-5.5

TQFP52

�40�C to 85�C

uPSD3233BV-24T6

24

128K

32K

8K

37

No

No

3.0-3.6

TQFP52

�40�C to 85�C

uPSD3233B-40U6

40

128K

32K

8K

46

No

Yes

4.5-5.5

TQFP80

�40�C to 85�C

uPSD3233BV-24U6

24

128K

32K

8K

46

No

Yes

3.0-3.6

TQFP80

�40�C to 85�C

uPSD3234A-40T6

40

256K

32K

8K

37

Yes

No

4.5-5.5

TQFP52

�40�C to 85�C

uPSD3234A-40U6

40

256K

32K

8K

46

Yes

Yes

4.5-5.5

TQFP80

�40�C to 85�C

uPSD3234BV-24U6

24

256K

32K

8K

46

No

Yes

3.0-3.6

TQFP80

�40�C to 85�C

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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

52-PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

XRAM-DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Boolean Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Relative Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Machine Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

uPSD3200 HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

External Int0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Timer 0 and 1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Timer 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

I

2

C Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

External Int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

DDC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

USB Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

USART Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Interrupt Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Interrupts Enable Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

POWER-SAVING MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

4/170

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Power Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

I/O PORTS (MCU MODULE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

PORT Type and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

SUPERVISORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Low VDD Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Watchdog Timer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

USB Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Timer 0 and Timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

STANDARD SERIAL INTERFACE (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Multiprocessor Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Serial Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

PULSE WIDTH MODULATION (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4-channel PWM Unit (PWM 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Programmable Period 8-bit PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

PWM 4 Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

I

2

C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Serial Status Register (SxSTA: S1STA, S2STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Data Shift Register (SxDAT: S1DAT, S2DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Address Register (SxADR: S1ADR, S2ADR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

DDC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Special Function Register for the DDC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Host Type Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

DDC1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

DDC2B Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

USB HARDWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

USB related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Receiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

External USB Pull-Up Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . 98

PSD MODULE DETAILED OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

MEMORY BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 99

Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

The Turbo Bit in PSD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

I/O PORTS (PSD MODULE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Document Outline

• FEATURES SUMMARY
  • Figure 1. Packages
  • Table 1. Device Summary
• SUMMARY DESCRIPTION
  • Figure 2. Block Diagram
  • Figure 3. TQFP52 Connections
  • Figure 4. TQFP80 Connections
  • Table 2. 80-Pin Package Pin Description
• 52-PIN PACKAGE I/O PORT
• ARCHITECTURE OVERVIEW
  • Memory Organization
    • Figure 5. Memory Map and Address Space
  • Registers
    • Figure 6. 8032 MCU Registers
    • Figure 7. Configuration of BA 16-bit Registers
    • Figure 8. Stack Pointer
    • Figure 9. PSW (Program Status Word) Register
  • Program Memory
  • Data memory
  • RAM
    • Figure 10. Interrupt Location of Program Memory
  • XRAM-DDC
  • XRAM-PSD
  • SFR
    • Table 3. RAM Address
  • Addressing Modes
    • Figure 11. Direct Addressing
    • Figure 12. Indirect Addressing
    • Figure 13. Indexed Addressing
  • Arithmetic Instructions
    • Table 4. Arithmetic Instructions
  • Logical Instructions
    • Table 5. Logical Instructions
  • Data Transfers
    • Table 6. Data Transfer Instructions that Access Internal Data Memory Space
    • Table 7. Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes)
    • Table 8. Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes)
    • Table 9. Shifting a BCD Number One Digit to the Right
    • Table 10. Data Transfer Instruction that Access External Data Memory Space
    • Table 11. Lookup Table READ Instruction
  • Boolean Instructions
    • Table 12. Boolean Instructions
  • Relative Offset
  • Jump Instructions
    • Table 13. Unconditional Jump Instructions
  • Machine Cycles
    • Table 14. Conditional Jump Instructions
    • Figure 14. State Sequence in uPSD323X Devices
• uPSD3200 HARDWARE DESCRIPTION
  • Figure 15. uPSD323X Devices Functional Modules
• MCU MODULE DISCRIPTION
  • Special Function Registers
    • Table 15. SFR Memory Map
    • Table 16. List of all SFR
    • Table 17. PSD Module Register Address Offset
• INTERRUPT SYSTEM
  • External Int0
  • Timer 0 and 1 Interrupts
  • Timer 2 Interrupt
  • I2C Interrupt
  • External Int1
  • DDC Interrupt
  • USB Interrupt
  • USART Interrupt
    • Figure 16. Interrupt System
    • Table 18. SFR Register
  • Interrupt Priority Structure
  • Interrupts Enable Structure
    • Table 19. Priority Levels
    • Table 20. Description of the IE Bits
    • Table 21. Description of the IEA Bits
    • Table 22. Description of the IP Bits
    • Table 23. Description of the IPA Bits
  • How Interrupts are Handled
    • Table 24. Vector Addresses
• POWER-SAVING MODE
  • Idle Mode
  • Power-Down Mode
    • Table 25. Power-Saving Mode Power Consumption
  • Power Control Register
    • Table 26. Pin Status During Idle and Power-down Mode
    • Table 27. Description of the PCON Bits
  • Idle Mode
  • Power-Down Mode
• I/O PORTS (MCU MODULE)
  • Table 28. I/O Port Functions
  • Table 29. P1SFS (91H)
  • Table 30. P3SFS (93H)
  • Table 31. P4SFS (94H)
  • PORT Type and Description
    • Figure 17. PORT Type and Description (Part 1)
    • Figure 18. PORT Type and Description (Part 2)
• OSCILLATOR
  • Figure 19. Oscillator
• SUPERVISORY
  • Figure 20. RESET Configuration
  • External Reset
  • Low VDD Voltage Reset
  • Watchdog Timer Overflow
  • USB Reset
• WATCHDOG TIMER
  • Table 32. Watchdog Timer Key Register (WDKEY: 0AEH)
  • Table 33. Description of the WDKEY Bits
  • Figure 21. RESET Pulse Width
  • Table 34. Watchdog Timer Clear Register (WDRST: 0A6H)
  • Table 35. Description of the WDRST Bits
• TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2)
  • Timer 0 and Timer 1
    • Table 36. Control Register (TCON)
    • Table 37. Description of the TCON Bits
    • Table 38. TMOD Register (TMOD)
    • Table 39. Description of the TMOD Bits
    • Figure 22. Timer/Counter Mode 0: 13-bit Counter
    • Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload
    • Figure 24. Timer/Counter Mode 3: Two 8-bit Counters
  • Timer 2
    • Table 40. Timer/Counter 2 Control Register (T2CON)
    • Table 41. Description of the T2CON Bits
    • Table 42. Timer/Counter2 Operating Modes
    • Figure 25. Timer 2 in Capture Mode
    • Figure 26. Timer 2 in Auto-Reload Mode
• STANDARD SERIAL INTERFACE (UART)
  • Multiprocessor Communications
  • Serial Port Control Register
    • Table 43. Serial Port Control Register (SCON)
    • Table 44. Description of the SCON Bits
    • Table 45. Timer 1-Generated Commonly Used Baud Rates
    • Figure 27. Serial Port Mode 0, Block Diagram
    • Figure 28. Serial Port Mode 0, Waveforms
    • Figure 29. Serial Port Mode 1, Block Diagram
    • Figure 30. Serial Port Mode 1, Waveforms
    • Figure 31. Serial Port Mode 2, Block Diagram
    • Figure 32. Serial Port Mode 2, Waveforms
    • Figure 33. Serial Port Mode 3, Block Diagram
    • Figure 34. Serial Port Mode 3, Waveforms
• ANALOG-TO-DIGITAL CONVERTOR (ADC)
  • ADC Interrupt
    • Figure 35. A/D Block Diagram
    • Table 46. ADC SFR Memory Map
    • Table 47. Description of the ACON Bits
    • Table 48. ADC Clock Input
• PULSE WIDTH MODULATION (PWM)
  • 4-channel PWM Unit (PWM 0-3)
    • Figure 36. Four-Channel 8-bit PWM Block Diagram
    • Table 49. PWM SFR Memory Map
  • Programmable Period 8-bit PWM
    • Figure 37. Programmable PWM 4 Channel Block Diagram
  • PWM 4 Channel Operation
    • Figure 38. PWM 4 With Programmable Pulse Width and Frequency
• I2C INTERFACE
  • Figure 39. Block Diagram of the I2C Bus Serial I/O
  • Table 50. Serial Control Register (SxCON: S1CON, S2CON)
  • Table 51. Description of the SxCON Bits
  • Table 52. Selection of the Serial Clock Frequency SCL in Master Mode
  • Serial Status Register (SxSTA: S1STA, S2STA)
  • Data Shift Register (SxDAT: S1DAT, S2DAT)
    • Table 53. Serial Status Register (SxSTA)
    • Table 54. Description of the SxSTA Bits
    • Table 55. Data Shift Register (SxDAT: S1DAT, S2DAT)
  • Address Register (SxADR: S1ADR, S2ADR)
    • Table 56. Address Register (SxADR)
    • Table 57. Start /Stop Hold Time Detection Register (S1SETUP, S2SETUP)
    • Table 58. System Cock of 40MHz
    • Table 59. System Clock Setup Examples
• DDC INTERFACE
  • Figure 40. DDC Interface Block Diagram
  • Special Function Register for the DDC Interface
    • Table 60. DDC SFR Memory Map
    • Table 61. Description of the DDCON Register Bits
    • Table 62. SWNEB Bit Function
  • Host Type Detection
    • Figure 41. Host Type Detection
  • DDC1 Protocol
    • Figure 42. Transmission Protocol in the DDC1 Interface
  • DDC2B Protocol
    • Figure 43. Conceptual Structure of the DDC Interface
• USB HARDWARE
  • USB related registers
    • Table 63. USB Address Register (UADR: 0EEh)
    • Table 64. Description of the UADR Bits
    • Table 65. USB Interrupt Enable Register (UIEN: 0E9h)
    • Table 66. Description of the UIEN Bits
    • Table 67. USB Interrupt Status Register (UISTA: 0E8h)
    • Table 68. Description of the UISTA Bits
    • Table 69. USB Endpoint0 Transmit Control Register (UCON0: 0EAh)
    • Table 70. Description of the UCON0 Bits
    • Table 71. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh)
    • Table 72. Description of the UCON1 Bits
    • Table 73. USB Control Register (UCON2: 0ECh)
    • Table 74. Description of the UCON2 Bits
    • Table 75. USB Endpoint0 Status Register (USTA: 0EDh)
    • Table 76. Description of the USTA Bits
    • Table 77. USB Endpoint0 Data Receive Register (UDR0: 0EFh)
    • Table 78. USB Endpoint0 Data Transmit Register (UDT0: 0E7h)
    • Table 79. USB Endpoint1 Data Transmit Register (UDT1: 0E6h)
    • Table 80. USB SFR Memory Map
  • Transceiver
    • Figure 44. Low Speed Driver Signal Waveforms
  • Receiver Characteristics
    • Figure 45. Differential Input Sensitivity Over Entire Common Mode Range
  • External USB Pull-Up Resistor
    • Figure 46. USB Data Signal Timing and Voltage Levels
    • Figure 47. Receiver Jitter Tolerance
    • Figure 48. Differential to EOP Transition Skew and EOP Width
    • Figure 49. Differential Data Jitter
    • Table 81. Transceiver DC Characteristics
    • Table 82. Transceiver AC Characteristics
• PSD MODULE
  • Functional Overview
    • Figure 50. PSD Module Block Diagram
  • In-System Programming (ISP)
    • Table 83. Methods of Programming Different Functional Blocks of the PSD Module
• DEVELOPMENT SYSTEM
  • Figure 51. PSDsoft Express Development Tool
• PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET
  • Table 84. Register Address Offset
• PSD MODULE DETAILED OPERATION
• MEMORY BLOCKS
  • Primary Flash Memory and Secondary Flash memory Description
  • Memory Block Select Signals
  • Instructions
    • Table 85. Instructions
  • Power-down Instruction and Power-up Mode
  • READ
    • Table 86. Status Bit
  • Programming Flash Memory
    • Figure 52. Data Polling Flowchart
    • Figure 53. Data Toggle Flowchart
  • Erasing Flash Memory
  • Specific Features
    • Table 87. Sector Protection/Security Bit Definition � Flash Protection Register
    • Table 88. Sector Protection/Security Bit Definition � Secondary Flash Protection Register
  • SRAM
  • Sector Select and SRAM Select
    • Figure 54. Priority Level of Memory and I/O Components in the PSD Module
    • Table 89. VM Register
    • Figure 55. Separate Space Mode
    • Figure 56. Combined Space Mode
  • Page Register
    • Figure 57. Page Register
• PLDs
  • Table 90. DPLD and CPLD Inputs
  • The Turbo Bit in PSD Module
    • Figure 58. PLD Diagram
  • Decode PLD (DPLD)
    • Figure 59. DPLD Logic Array
  • Complex PLD (CPLD)
    • Figure 60. Macrocell and I/O Port
  • Output Macrocell (OMC)
    • Table 91. Output Macrocell Port and Data Bit Assignments
  • Product Term Allocator
    • Figure 61. CPLD Output Macrocell
  • Input Macrocells (IMC)
    • Figure 62. Input Macrocell
• I/O PORTS (PSD MODULE)
  • General Port Architecture
    • Figure 63. General I/O Port Architecture
  • Port Operating Modes
  • MCU I/O Mode
  • PLD I/O Mode
  • Address Out Mode
  • Peripheral I/O Mode
  • JTAG In-System Programming (ISP)
    • Figure 64. Peripheral I/O Mode
    • Table 92. Port Operating Modes
    • Table 93. Port Operating Mode Settings
    • Table 94. I/O Port Latched Address Output Assignments
  • Port Configuration Registers (PCR)
    • Table 95. Port Configuration Registers (PCR)
    • Table 96. Port Pin Direction Control, Output Enable P.T. Not Defined
    • Table 97. Port Pin Direction Control, Output Enable P.T. Defined
    • Table 98. Port Direction Assignment Example
  • Port Data Registers
    • Table 99. Drive Register Pin Assignment
    • Table 100. Port Data Registers
  • Ports A and B � Functionality and Structure
    • Figure 65. Port A and Port B Structure
  • Port C � Functionality and Structure
    • Figure 66. Port C Structure
  • Port D � Functionality and Structure
    • Figure 67. Port D Structure
  • External Chip Select
    • Figure 68. Port D External Chip Select Signals
• POWER MANAGEMENT
  • Figure 69. APD Unit
  • Figure 70. Enable Power-down Flow Chart
  • Table 101. Power-down Mode�s Effect on Ports
  • PLD Power Management
  • PSD Chip Select Input (CSI, PD2)
  • Input Clock
  • Input Control Signals
    • Table 102. Power Management Mode Registers PMMR0
    • Table 103. Power Management Mode Registers PMMR2
    • Table 104. APD Counter Operation
• RESET TIMING AND DEVICE STATUS AT RESET
  • Warm RESET
  • I/O Pin, Register and PLD Status at RESET
  • Reset of Flash Memory Erase and Program Cycles
    • Figure 71. Reset (RESET) Timing
    • Table 105. Status During Power-on RESET, Warm RESET and Power-down Mode
• PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
  • Standard JTAG Signals
    • Table 106. JTAG Port Signals
  • JTAG Extensions
  • Security and Flash memory Protection
• INITIAL DELIVERY STATE
• AC/DC PARAMETERS
  • Figure 72. PLD ICC /Frequency Consumption (5V range)
  • Figure 73. PLD ICC /Frequency Consumption (3V range)
  • Table 107. PSD Module Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off)
• MAXIMUM RATING
  • Table 108. Absolute Maximum Ratings
• EMC CHARACTERISTICS
  • Functional EMS (Electromagnetic Susceptibility)
  • Designing Hardened Software To Avoid Noise Problems
  • Absolute Maximum Ratings (Electrical Sensitivity)
    • Table 109. EMS Test Results
    • Table 110. ESD Absolute Maximum Ratings
    • Table 111. Latch-up and Dynamic Latch-up Electrical Sensitivities
• DC AND AC PARAMETERS
  • Table 112. Operating Conditions (5V Devices)
  • Table 113. Operating Conditions (3V Devices)
  • Table 114. AC Letter Symbols for Timing
  • Table 115. AC Signal Behavior Symbols for Timing
  • Figure 74. Switching Waveforms � Key
  • Table 116. Major Parameters
  • Table 117. DC Characteristics (5V Devices)
  • Table 118. DC Characteristics (3V Devices)
  • Figure 75. External Program Memory READ Cycle
  • Table 119. External Program Memory AC Characteristics (with the 5V MCU Module)
  • Table 120. External Program Memory AC Characteristics (with the 3V MCU Module)
  • Table 121. External Clock Drive (with the 5V MCU Module)
  • Table 122. External Clock Drive (with the 3V MCU Module)
  • Figure 76. External Data Memory READ Cycle
  • Figure 77. External Data Memory WRITE Cycle
  • Table 123. External Data Memory AC Characteristics (with the 5V MCU Module)
  • Table 124. External Data Memory AC Characteristics (with the 3V MCU Module)
  • Table 125. A/D Analog Specification
  • Figure 78. Input to Output Disable / Enable
  • Table 126. CPLD Combinatorial Timing (5V Devices)
  • Table 127. CPLD Combinatorial Timing (3V Devices)
  • Figure 79. Synchronous Clock Mode Timing � PLD
  • Table 128. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)
  • Table 129. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)
  • Figure 80. Asynchronous RESET / Preset
  • Figure 81. Asynchronous Clock Mode Timing (product term clock)
  • Table 130. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
  • Table 131. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)
  • Figure 82. Input Macrocell Timing (product term clock)
  • Table 132. Input Macrocell Timing (5V Devices)
  • Table 133. Input Macrocell Timing (3V Devices)
  • Table 134. Program, WRITE and Erase Times (5V Devices)
  • Table 135. Program, WRITE and Erase Times (3V Devices)
  • Figure 83. Peripheral I/O READ Timing
  • Table 136. Port A Peripheral Data Mode READ Timing (5V Devices)
  • Table 137. Port A Peripheral Data Mode READ Timing (3V Devices)
  • Figure 84. Peripheral I/O WRITE Timing
  • Table 138. Port A Peripheral Data Mode WRITE Timing (5V Devices)
  • Table 139. Port A Peripheral Data Mode WRITE Timing (3V Devices)
  • Figure 85. Reset (RESET) Timing
  • Table 140. Reset (RESET) Timing (5V Devices)
  • Table 141. Reset (RESET) Timing (3V Devices)
  • Table 142. VSTBYON Definitions Timing (5V Devices)
  • Table 143. VSTBYON Timing (3V Devices)
  • Figure 86. ISC Timing
  • Table 144. ISC Timing (5V Devices)
  • Table 145. ISC Timing (3V Devices)
  • Figure 87. MCU Module AC Measurement I/O Waveform
  • Figure 88. PSD Module AC Float I/O Waveform
  • Figure 89. External Clock Cycle
  • Figure 90. Recommended Oscillator Circuits
  • Figure 91. PSD Module AC Measurement I/O Waveform
  • Figure 92. PSD ModuleAC Measurement Load Circuit
  • Table 146. Capacitance
• PACKAGE MECHANICAL INFORMATION
  • Figure 93. TQFP52 � 52-lead Plastic Thin, Quad, Flat Package Outline
  • Table 147. TQFP52 � 52-lead Plastic Thin, Quad, Flat Package Mechanical Data
  • Figure 94. TQFP80 � 80-lead Plastic Thin, Quad, Flat Package Outline
  • Table 148. TQFP80 � 80-lead Plastic Thin, Quad, Flat Package Mechanical Data
• PART NUMBERING
  • Table 149. Ordering Information Scheme
• REVISION HISTORY
  • Table 150. Document Revision History
  • Table 151. Device Functional Change History